Design of ultra low power analog-to-digital converter for ambulatory EEG recording

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2012.Cataloged from PDF version of thesis.Includes bibliographical references (p. 65-67).Portable acquisition of biopotential signals requires the design of compact, energy efficient circuits and systems. Such systems typically include analog-to-digital converter for digitizing signals from AFE and feeding it to DBE. An Ultra low power ADC is designed in this work to be integrated within scalable EEG SoC. The full system can capture EEG signals through 1 up to 8 parallel differential channels that are time division multiplexed into a single ADC. The ADC has a fixed resolution of 10 bits which is sufficient for extraction of bio-markers for seizure detection. A SAR ADC architecture is chosen for this design as it is highly energy efficient for medium to high resolution applications with low speed requirements. A differential capacitive DAC is utilized to enhance the CMRR. Concepts of split-capacitor array and sub-DAC are combined to reduce the DAC area and power consumption. Charge pumps are used to boost the control voltage of sampling switches. The ADC performs a conversion every 16 clock cycle while being governed by a self-resetting SAR logic. The sampling rate can be scaled up to 32 kHz by varying the clock frequency to accommodate different number of channels used. The ADC was designed and fabricated in a 0.18 pm CMOS technology. The entire ADC core consumes 1 pW from 1 V supply at a sampling rate of 32 kHz. The ADC has a maximum DNL and INL of 0.55 LSB and 0.75 LSB respectively. The SNDR and SFDR of the converter are measured at a sampling rate of 32 kHz and 15.5 kHz input tone to be 57.9 dB and 68.5 dBFS respectively. The ADC FOM is 51 fJ/Conv-Step.by Dina Reda El-Damak.S.M

A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors

Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection

Prolonged energy harvesting for ingestible devices

Ingestible electronics have revolutionized the standard of care for a variety of health conditions. Extending the capacity and safety of these devices, and reducing the costs of powering them, could enable broad deployment of prolonged-monitoring systems for patients. Although previous biocompatible power-harvesting systems for in vivo use have demonstrated short (minute-long) bursts of power from the stomach, little is known about the potential for powering electronics in the longer term and throughout the gastrointestinal tract. Here, we report the design and operation of an energy-harvesting galvanic cell for continuous in vivo temperature sensing and wireless communication. The device delivered an average power of 0.23 μW mm⁻² of electrode area for an average of 6.1 days of temperature measurements in the gastrointestinal tract of pigs. This power-harvesting cell could provide power to the next generation of ingestible electronic devices for prolonged periods of time inside the gastrointestinal tract.National Institutes of Health (U.S.) (Grant EB-000244

Power management circuits for ultra-low power systems

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2015.Cataloged from PDF version of thesis.Includes bibliographical references (pages 137-145).Power management circuits perform a wide range of vital tasks for electronic systems including DC-DC conversion, energy harvesting, battery charging and protection as well as dynamic voltage scaling. The impact of the efficiency of the power management circuits is highly profound for ultra-low power systems such as implantable, ingestible or wearable devices. Typically the size of the system for such applications does not allow the integration of a large energy storage device. Therefore, extreme energy efficiency of the power management circuits is critical for extended operation time. In addition, flexibility and small form factor are desirable to conform to the human body and reduce the system's over all size. Thus, this thesis presents highly efficient and miniature power converters for multiple applications using architecture and circuit level optimization as well as emerging technologies. The first part presents a power management IC (PMIC) featuring an integrated reconfigurable switched capacitor DC-DC converter using on-chip ferroelectric caps in 130 nm CMOS process. Digital pulse frequency modulation and gain selection circuits allow for efficient output voltage regulation. The converter utilizes four gain settings (1, 2/3, 1/2, 1/3) to support an output voltage of 0.4 V to 1.1 V from 1.5 V input while delivering load current of 20 [mu]A to 1 mA. The PMIC occupies 0.366 mm² and achieves a peak efficiency of 93% including the control circuit overhead at a load current of 500 [mu]A. The second part presents a solar energy harvesting system with 3.2 nW overall quiescent power. The chip integrates self-startup, battery management, supplies 1 V regulated rail with a single inductor and supports power range of 10 nW to 1 [mu]W. The control circuit is designed in an asynchronous fashion that scales the effective switching frequency of the converter with the level of the power transferred. The ontime of the converter switches adapts dynamically to the input and output voltages for peak-current control and zero-current switching. The system has been implemented in 180 nm CMOS process. For input power of 500 nW, the proposed system achieves an efficiency of 82%, including the control circuit overhead, while charging a battery at 3 V from 0.5 V input. The third part focuses on developing an energy harvesting system for an ingestible device using gastric acid. An integrated switched capacitor DC-DC converter is designed to efficiently power sensors and RF transmitter with a 2.5 V regulated voltage rail. A reconfigurable Dickson topology with four gain settings (3, 4, 6, 10) is used to support a wide input voltage range from 0.3 V to 1.1 V. The converter is designed in 65 nm CMOS process and achieves a peak efficiency of 80% in simulation for output power of 2 [mu]W. The last part focuses on flexible circuit design using Molybdenum Disulfide (MoS₂), one of the emerging 2D materials. A computer-aided design flow is developed for MoS₂-based circuits supporting device modeling, circuit simulation and parametric cell-based layout - which paves the road for the realization of large-scale flexible MoS₂ systems.by Dina Reda El-Damak.Ph. D